Changes between Initial Version and Version 1 of Ticket #344, comment 1


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Timestamp:
01/11/2025 04:35:45 PM (19 months ago)
Author:
canthony

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  • Ticket #344, comment 1

    initial v1  
    1010
    1111The second CPU 1 fault on the third line would only happen if the cam_clear loop timed out and reissued the connects; the lack of CPUs 2 and 3 messages suggests that they did not get a chance to respond in time.
     12
     13The source of the connects could only have been cam_clear since the history debugger log showed that all of the processors were involved in cam_clear or wired_fim connect handler.