Opened 8 months ago
#384 new defect
config deck parser doesn't understand that L68 CPUs have 2 bit CPU numbers.
| Reported by: | canthony | Owned by: | Eric Swenson |
|---|---|---|---|
| Priority: | minor | Milestone: | |
| Component: | Hardcore | Version: | |
| Keywords: | config deck, L68 | Cc: |
Description
On DPS8M CPUs, the configuration panel has a 3 bit "CPU number" setting, allowing the number to be set from 0 to 7 (A-H).
On L68 CPUs, it is a 2 bit number, so L68 CPUs are numbered 0-3 (A-D).
The RSW,2 instruction is used to read the CPU number switch settings. On L68, the value is returned in bits 34-35; on DPS8M in bits 33-35.
When Multics starts the CPU. the switch setting is compared to the CPU config card; if they do not match, the CPU is not started.
When ISOLTS starts the test CPU, the same check is made.
The switch settings are cosmetic; they are checked to make sure that operations can locate the correct cabinet if Multics/ISOLTS/T&D directs them to a particular CPU.
Because L68 CPUs have a two bit CPU number, they cannot pass the value check if that are configured as E, F, G or H.
The config deck parser should generate a warning if a CPU config deck CPU card specifies a L68 model and a D, E, F or G tag.
